In electronic systems, clocks and carriers abound. They are the heartbeat of synchronous circuits such as microprocessors. They are used to construct communications signals for transmission, and to recover data from received signals. They regulate the sampling of continuous-time signals, and the conversion of discrete-time signals into continuous-time form. They are modulated to carry information in elevated frequency bands, and are instrumental in demodulation.
Clock quality has a direct bearing on system performance, e.g. operating margin, signal-to-noise ratio, spectral efficiency etcetera. Applications involving e.g. digital audio signals or radio-frequency communications can place particularly stringent limits on clock jitter and carrier phase noise. Aspects relating to flexibility and cost are also very important in most applications.
It is a common desire or requirement that a clock be synchronized to another clock, or to a timing reference of more general form. This applies for example when digital audio and video signals are communicated in real time. The design of clock synchronizing circuits is an established field, and many types of clock synchronizer are known within the art. Examples include various classes of phase-locked loop (PLL), direct digital synthesizer (DDS) and anti-jitter circuit (AJC).
Clock synchronization encompasses phase locking, frequency locking and frequency ratio locking. Hence it includes reference-locked frequency synthesis.
In phase-locked loops, the clock is provided by a controllable oscillator that is pulled into lock by the action of feedback. The feedback path optionally includes a frequency divider. A phase detector compares the divided clock with the timing reference, and generates an error signal representing their phase offset. This error signal drives a loop filter, the output of which is connected to the oscillator's frequency control port.
Below the PLL's closed-loop corner frequency, jitter on the timing reference passes straight to the clock. Above its corner frequency, the oscillator's intrinsic jitter passes straight to the clock. In setting the loop bandwidth the designer must find a compromise between the need for good reference jitter attenuation and the need for low PLL intrinsic jitter. If a high-Q oscillator is used, such as a voltage-controlled crystal oscillator (VCXO), the PLL can have narrow bandwidth and low jitter. However, VCXOs can be pulled only over a narrow frequency range. Also, they are relatively expensive and cannot be implemented on chip. Conversely, low-Q oscillators such as ring oscillators have wide frequency range and are fully integrable, but their high self-noise and their sensitivity to interference makes them only suited to use in wide-bandwidth PLLs.
When the timing reference is clean and fast, there is no problem with using a wide-bandwidth PLL. This is the case in many standalone frequency synthesizers, for example, where the reference is typically a local crystal oscillator. However, it is not the case in most other applications. The timing reference is often a low-rate signal, e.g. because of limited capacity in the channel from the timing master. Also it is often of relatively low quality, due to imperfect characteristics of that channel.
Frame locking is also a requirement in many systems. This too has tended to keep the rate of timing reference signals down. Many de-facto timing references consist only of a framing component, on the basis that this is all that is needed. Frame rates are often quite low, e.g. 8 kHz in telecom systems.
One way of constructing a clock synchronizer that can meet the conflicting requirements outlined above would be to make use of direct digital synthesis (DDS). In direct digital synthesizers a numeric oscillator generates a digital representation of a sinewave which is then passed through a digital-to-analog converter (DAC), filtered to remove spuriae, and compared with a DC value to create the desired squarewave. However, DDS is not without problems. One is the cost of the DAC. Others relate to finite wordlength effects, inadequate reconstruction filtering, and susceptibility to interference at the point where the sinewave is turned into a squarewave.
The cost of the DAC, the filter and the comparator can be avoided by taking the sign of the numeric oscillator's output, and using that as the clock. However, such number-controlled oscillators (NCOs) suffer greatly from beat-frequency effects. Superior number-controlled oscillators are known within the art, but even they have certain shortcomings. Wholly numeric PLLs constructed around such oscillators generally suffer from an excess of high-frequency jitter, compared with analog PLLs. On the other hand, they are easy to test, need no calibration, have great repeatability, and present the opportunity to add many advanced features at little incremental cost. For example, accurate frequency holdover is straightforward with numeric PLLs, and rapid locking, e.g. by bandwidth adaption, poses far fewer problems than in analog.
An object of the invention may include one or several of the below-stated provisions of:                A clock synchronizer/synthesizer that has high performance, high flexibility and low implementation cost.        A clock synchronizer/synthesizer that achieves the high performance of VCXO-based PLLs without incurring the cost of a VCXO.        A clock synchronizer/synthesizer that has less low-frequency intrinsic jitter (close-in phase noise) than VCXO-based PLLs.        A clock synchronizer/synthesizer that has narrow bandwidth, low intrinsic jitter and a wide range of operating frequencies.        A narrow-bandwidth low-jitter wide-range clock synchronizer/synthesizer that can smoothly track large changes in reference frequency.        A ring-oscillator-based clock synchronizer/synthesizer that has higher performance than previous ring-oscillator-based clock synchronizers/synthesizers.        A clock synchronizer/synthesizer that is readily integrable on chip using common processes and building blocks.        A clock synchronizer/synthesizer that is less sensitive to interference and layout than previous clock synchronizers.        A clock synchronizer/synthesizer that combines the good features of numeric PLLs with the good features of analog PLLs.        A clock synchronizer/synthesizer that achieves the performance and flexibility of DDS-based clock synchronizers without incurring the cost of a DAC.        A number-controlled oscillator that has higher performance, higher flexibility and lower cost than previous number-controlled oscillators.        An asynchrony detector that has novel capabilities relating to frame locking.        